System on a chip (SoC) devices are becoming more prevalent in today's high tech world. SoCs incorporate a large amount of processing functionality with heterogeneous devices on a single semiconductor device. As SoCs become more complicated over time, efficient and low overhead power management becomes more difficult as the number of subsystems expands. The latency to enter and exit low power states is a key parameter effecting power management efficiency of SoCs. The transition time of subsystems going into and out of a low power state effectively gets removed from the residency time of the SoCs in the low power state, thereby resulting in higher power consumption and shorter battery life.